The invention relates to technology for performing electrical analysis of an electronic design.
A field solver is often used to perform electrical analysis of a design. A field solver comprises software and/or hardware that translates a geometric description of conductor and insulator objects, or other shapes described in an IC design file or database, to associated parasitic capacitances values. The capacitance values may include total capacitance of a single conductor, defined as the source conductor, relative to neighboring conductors or separate coupling capacitance between the source and one or more neighboring conductors.
Electromagnetic (EM) characterization equations used in field solvers typically require significant compute time to solve the capacitance for a given set of geometric properties but are highly accurate. However, the computation time is often too burdensome to allow the field solver to be used to compute parasitic capacitance for significant regions of a conventional integrated circuit (IC) design.
One possible approach to address this problem is to generate field solver computed capacitance and resistance data for a limited number of test cases consisting of specific geometric descriptions of conductors. These test cases are then used to create an estimator of the capacitance and resistance, which is called an extractor or parasitic resistance and capacitance (RC) extraction component. However, the models in this approach are created with little or no knowledge of the specific types of design geometries the models will most likely encounter, and therefore analysis using these models is likely to produce sub-optimal results.